Electrical Through-Wafer Interconnects for Integrated Sensors and Actuators


In micro-electro-mechanical-systems (MEMS) applications, it is advantageous to have electronic circuitry as near the sensor/actuator as possible. However, integrating both the MEMS devices with electronics on the same wafer often leads to a compromise between the performance of either or both systems. An excellent solution to this problem is to construct the optimum MEMS devices and electronics on separate wafers, provides a through wafer interconnect (via) with minimum resistance and capacitance on the MEMS wafer, then flip-chip bond the two wafers. In this fashion, the MEMS wafer can be fully populated with very high fill factor such as in applications of infra-red (IR) focal plane arrays, spatial light modulator (SLM) of adaptive optics, and three-dimensional ultrasound imaging. Finally, since the MEMS and electronics wafers can be fabricated in different facilities, the overall yield of the manufacturing process is enhanced. The through-wafer interconnect presents a parallel capacitance and a series resistance to the input impedance of the MEMS device. Thus, for operation that is not limited by the interconnect, both the capacitance and resistance have to be very small. A technology for high density and low parasitic capacitance electrical through-wafer interconnects to an array of micromachined transducers on a silicon wafer is presented here. Vertical through-wafer interconnects with high aspect ratio connect an array of sensors or actuators from the front side (transducer side) to the backside (packaging side) of the wafer. Reduction of the parasitic capacitance to the substrate is achieved using the reverse-biased pn junction diode or metal insulator semiconductor (MIS) configuration for applications requiring higher breakdown voltage of isolation. Integrations of both surface micromachined and SOI wafer bonded MEMS devices have been demonstrated. This three-dimensional architecture allows for elegant packaging through simple flip-chip bonding of the chip’s backside to an ASIC, fan out chip, or printed circuit board (PCB).

 

Back