Interconnection Schemes for Large Transducer Arrays

To integrate densely populated arrays with associated transmit/receive electronics, several interconnection schemes have been proposed. Monolithic integration of CMUTs with electronic circuits has also been proposed [1]. Monolithic integration usually compromises the performance of one or both components. A modified CMOS or BiCMOS process can be used to fabricate ultrasonic transducers on the same silicon substrate with electronic circuits [1, 2]. Although cost-effective, it is not suitable for arrays with tight area constraints because the usable active area is compromised by the electronics and the number of available design parameters is reduced for a standard process. An alternate method uses post-processing to fabricate CMUT elements over the electronics chip, built using a standard CMOS process [3, 4]. The wafer with electronics undergoes passivation and CMP processes before CMUT fabrication. This integration method, probably slightly costlier than the former, is suitable for 2-D array integration because of its better area utilization. Because pre-processed electronics limits the temperature of post-processes, a low temperature process must be used to fabricate CMUTs over the electronics. Although this process, which uses plasma enhanced chemical vapor deposition (PECVD), has been tailored to achieve good control over membrane stress and reasonable uniformity, the high temperature CMUT process, which uses low-pressure chemical vapor deposition (LPCVD), still produces better on-wafer and wafer-to-wafer uniformity and higher yield.

Our group has developed two techniques, both based on the exploration of vertical dimension of the transducer arrays to address elements in large arrays.

 

Through-wafer via interconnects

 

In this approach, high-aspect ratio through-wafer vias are etched on silicon wafers before the fabrication of the transducers. Typical dimensions of these vias are 20 microns in diameter and 400 microns deep. Deep reactive ion etching is used to etch these vias from both sides of the silicon wafer. After the vias are etched through, an insulation oxide is thermally grown, followed by the back-filling of polysilicon and doping to reduce series resistance. The parallel parasitic capacitance of the interconnect is largely determined by the depletion width of the metal-insulator-semiconductor capacitor. Therefore, high resistivity silicon substrates are used to enhance the depletion width to reduce the parallel parasitic capacitance. In a variation of the approach, the thermal oxide is replaced by a reverse biased p-n junction. This is achieved by doping the via side walls with an appropriate dopant. The fabrications of the transducer elements on the front side and the flip-chip bond pads on the back side follow. Typically, the series resistance for these interconnects are about 20 Ω, and the parallel parasitic capacitance due to the via is about 60 fF. More details on this process can be found in [5].

 

Trench-isolated through-wafer interconnects

 

The more recent approach to solving the interconnect problem is based on the through-wafer trenches. Instead of etching vias and back filling them with conductive materials, the silicon substrate itself is used as the electrodes. In this approach, the transducers are fabricated on the wafer front side first, then, the wafer front side is attached to a carrier wafer, and through-wafer trenches are formed from the back side of the wafer. The wafer is then diced and flip-chip bonded to front-end electronics. At this point, the carrier wafer can be safely removed. The through-wafer trench isolated interconnect is compatible with both the surface-micromachined CMUTs and wafer-bonded CMUTs, and requires fewer process steps. The substrate of the transducer can be thinned down to push the substrate ringing out of the device band. Typically, the series resistance is less than 10 Ω when highly conductive silicon substrate is used. The element-to-element coupling capacitance is about 30 fF. More details on this process can be found in [6].

 

FIGURE 1. Cross-section of through-wafer via interconnects with gold studs in a CMUT/IC assembly (left). SEM cross section of the through wafer via interconnect (right).

 

FIGURE 2. Cross-section of trench isolated CMUTs with solder bumps bonded to IC.

 

 

Resources

 

[1] Eccardt PC, Niederer K, Scheiter T, and Hierhold C, “Surface micromachined ultrasound transducers in CMOS technology," Proceedings of the 1996 IEEE International Ultrasonics Symposium, pp. 959-962, 1996.

[2] Niederer K, Eccardt PC, Meixner H, and Lerch R, “Micromachined transducer design for minimized generation of surface waves," Proceedings of the 1999 IEEE International Ultrasonics Symposium, pp. 1137-1139, 1999.

[3] Noble RA, Davies RR, King DO, Day MM, Jones ARD, McIntosh JS, Hutchins DA, and Saul P, “Low temperature micromachined cMUTs with fully-integrated analogue front-end electronics,” Proceedings of IEEE International Ultrasonics Symposium, pp. 1045–1050, 2002.

[4] Daft C, Calmes S, da Graca D, Patel K, Wagner P, and Ladabaum I, “ Microfabricated ultrasonic transducers monolithically integrated with high voltage electronics,” Proceedings of IEEE International Ultrasonics Symposium, pp. 493–496, 2004.

[5] C. H. Cheng, A. S. Ergun, and B. T. Khuri-Yakub, “Electrical through-wafer interconnects with sub-picofarad parasitic capacitance,” in Microelectromechanical Systems Conference, 2001, pp. 18 – 21.

[6] X. Zhuang, et al, “Through-wafer trench-isolated electrical interconnects for CMUT arrays,” presented at 2005 IEEE Ultrasonics Symposium, Rotterdam, The Netherlands, September 19-21, 2005.

 

Acknowledgements

 

This project was funded by National Institutes of Health under grant CA99059 and by the Department of Navy under grant N00014-98-1-0634.