Sacrificial-Etch Fabrication Process for CMUTs

The first CMUTs were built using a sacrificial release process that has become the standard CMUT fabrication method [1, 2]. Numerous variations of the sacrificial release process have been published, all based on the same basic principle. The cavity underneath the membrane is created by depositing or growing a sacrificial layer on the carrier substrate. After the membrane deposition, the sacrificial layer is removed with an etchant, specifically chosen to etch the sacrificial layer material but not to etch the membrane layer material. A number of sacrificial layer, membrane, and substrate material combinations can be used to fabricate CMUTs. Although the fabrication method remains more or less the same, the combination of materials makes a difference in the design, process control, and overall device yield [3]

The CMUT fabrication process starts with a conductive silicon wafer. The silicon surface is doped with the appropriate dopant to achieve high conduction at the surface, which is the back electrode in CMUT operation. Silicon nitride is then deposited to form the etch-stop layer, which must be sufficiently thick to protect the silicon wafer from the etchant during the membrane release process. Because the capacitance of the etch-stop layer comes in series with the active gap capacitance it cannot be arbitrarily thick. In principle, only a few hundred Angstroms of LPCVD silicon nitride is sufficient: but typically a 0.1 µm thick etch-stop layer is used to avoid problems with possible pin holes in very thin silicon nitride layers.

Sacrificial layer deposition and patterning is done in two steps so that the channels that KOH uses to remove the sacrificial layer are thinner than the cavity thickness. In the first step, a layer of LPCVD poly-silicon is deposited, and regions of reduced channel height are defined by photolithography. The subsequent dry etch removes all the poly-silicon in the defined regions, but stops on the silicon nitride layer underneath (Fig. 1 (a)).

Another thin layer of poly-silicon deposition follows the first (Fig. 1 (b)). The thickness of the second poly-silicon layer determines the thickness of the channels and the total poly-silicon thickness from the first and second depositions determines the initial cavity height. For these two poly-silicon depositions that define the cavity and channel height, a low deposition temperature (560 oC) is preferred to allow better control over both thicknesses. Another photolithography and dry etch step follows the second poly-silicon deposition, defining the cavity and the membrane shape, together with the etch channels (Fig. 1 (c)). In general, the membrane can be any shape, but circles and hexagons are easier to model and used most often. Rectangular is also a popular membrane shape because of the better fill factor and average membrane displacement it offers. Both the shape and the size of the membrane are critical cMUT design parameters that determine the frequency response of the element.

The next step is the critical membrane deposition (Fig. 1 (d)). The membrane is made of silicon nitride deposited by LPCVD at 785 oC. The composition of the gasses is adjusted to obtain a low-stress silicon nitride film (dichlorisilabe (DCS) to ammonia (NH3) ratio of 14:1). Typically, the silicon nitride films deposited with such conditions have 100 MPa tensile stress and a refractive index of 2.4. Because there will be another layer of silicon nitride added during the sealing step, the silicon nitride thickness at this time is not the final membrane thickness. A lithography and dry etch step opens small holes through the silicon nitride layer (Fig. 1 (e)). The etch holes are located on the etch channels, so that when the wafer is immersed in KOH solution, KOH etches its way to the cavity and releases the membrane (Fig. 1 (f)).

 

 

The poly-silicon etch rate of KOH is highly dependent on temperature. At room temperature, the etch may take several days depending on the membrane size and height of the etch channels, which limit the diffusion of KOH. Near boiling point, the etch rate increases over on order of magnitude. However, the fast etch near boiling temperatures is not preferred because the etch selectivity between silicon nitride and poly-silicon gets worse. During the long KOH etch; the etch-stop layer protects the silicon wafer.

The process continues with the sealing of the etch holes with another layer of LPCVD silicon nitride deposition (Fig. 1 (g)). Because the sealing is done at low pressure deposition condition of the LPCVD (200 mTorr at 785 oC), the cavity is assumed to be vacuum sealed for practical purposes. The rest of the process involves getting the electrical connections from the bond pads to the top and bottom electrodes. A lithography and etch step opens a connection to the ground plane through the silicon nitride layer. Subsequently, aluminum is sputtered over the whole wafer, and patterned with lithography and wet etch (Fig. 1 (h)). Because of the conformal coverage it provides over the steps, sputtering is preferred for metal deposition. The final lithography and etch step defines the top electrode coverage over the membrane. After putting the metal, it is usually best to anneal the wafers at 450 oC in FGA to get ohmic contact to ground. However, high tensile stress generated in the Al electrode by annealing must be accounted for while designing the cMUT.

 

FIGURE 1. Sacrificial release process: (a) Substrate doping, etch-stop layer deposition (LPCVD silicon nitride), first sacrificial layer deposition (LPCVD poly-silicon) and patterning, (b) second sacrificial layer deposition for reduced etch channel height regions, (c) active area definition, (d) membrane deposition, (e) define sacrificial release etch holes and etch silicon nitride, (f) membrane release in KOH, (g) membrane sealing with more silicon nitride deposition, (h) top electrode deposition and patterning

 

 

Resources

 

[1] Jin X, Ladabaum I, and Khuri-Yakub BT, "The Microfabrication of Capacitive Ultrasonic Transducers," Journal of Microelectromechanical Systems, vol. 7, pp. 295-302, Sept. 1998.

[2] Jin X, Ladabaum I, Degertekin FL, Calmes S, and Khuri-Yakub BT, "Fabrication and Characterization of Surface Micromachined Capacitive Ultrasonic Immersion Transducers," Journal of Microelectromechnical Systems, vol. 8, pp. 100-114, March 1999.

[3] S. Ergun, Y. Huang, X. Zhuang, Ö. Oralkan, G. G. Yaralioglu, and B. T. Khuri-Yakub, “Capacitive micromachined ultrasonic transducers: fabrication technology,” IEEE Trans. Ultrason., Ferroelect., Freq. Contr., vol. 52, no. 12, pp. 2242-2258, Dec. 2005.

 

Acknowledgements

 

This work was supported by the U.S Office of Naval Research and National Institutes of Health.