Real-Time Data Acquisition and Beamforming System Design

We have an FPGA-based data acquisition and processing system (Lyrtech, Quebec City, QB, Canada) to implement a real-time 3-D beamformer (Fig. 1). This system includes 16-channel, 105-MSa/s, 14-bit ADCs for digitization of echo signals and a Xilinx Virtex II XC2V6000 FPGA for data processing. We programmed the system to acquire and process data from a single channel for the implementation of classical synthetic aperture beamforming. Currently, we are improving the system to handle 16 receive channels at a time, while generating the delay information for 224 transmit channels.

 

FIGURE 1. (a) Data acquisition system. (b) Data acquisition and processing board with 16 parallel ADCs and a dedicated FPGA.

 

FIGURE 2. System architecture.

Acknowledgements

This project was funded by National Institutes of Health under grant CA99059.